Cadence has introduced Command-Line IP Selector (CLIPS) support to provide a bridge between Virtuoso—a UI-based, analog, and mixed-signal design environment—and other command-line, digital, and mixed-signal simulation tools and flows that use a text-based setup. CLIPS can be used to import an AMS IP into an existing digital-centric verification setup.(read more)![]()
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Virtuoso Video Diary: Bridging Virtuoso and Mixed-Signal Simulation Tools Using CLIPS
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Virtuosity: How to Run a Multi-Technology Simulation (MTS)?
Are you looking for some hands-on experience with running multi-technology simulation in Virtuoso ADE Explorer and Virtuoso ADE Assembler?
In today’s fast-shrinking technology, we often have situations where we need to design custom IC system-in-packages (SiP). But, here comes the challenge – how to design these ICs using different technologies in a single design environment and analyze their responses when there are library name collisions along with the model name collisions.(read more)![]()
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Virtuoso IC6.1.7 ISR20 and ICADV12.3 ISR20 Now Available
The IC6.1.7 ISR20 and ICADV12.3 ISR20 production releases are now available for download. To find out more, click here…(read more)![]()
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Virtuosity: Let's Have Fun with ADE Debugging – Part 1
Over the years, we have seen our customers’ usage of ICRPs increase dramatically. It is now quite common to run 1000s of simulation points using 100s of ICRPs. And as this usage has increased, one of the challenges that has emerged is how to debug issues with ICRPs and job distribution, which is the topic of my write-up. So, what is it that I’m trying to address? Does the following sound familiar?
User hits green button in ADE, expects simulations to run and see results.
However, no simulation is starting. Why?
Or, one or more simulations fail, or, one or more measurements fail. User wants to find out what happened?
Or, things are running, but seem to take an excessive amount of time (usually not the actual simulation time, but rather setup time or time to obtain results).
How can we debug what’s wrong?
The objective of these slides is to equip everyone with a baseline set of tools and information to be used when investigating issues in ADE. These slides can serve as a very good reference material when faced with job distribution issues in ADE. Through this and my future blogs on debugging, I’ll attempt to use the tools and recipes from the slides and apply these to real life situations.(read more)![]()
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Virtuoso Video Diary: What's this Net Connected to?
Meet the Virtuoso Schematic Editor L Probes assistant, a dockable assistant where you can identify connections that exist for a net, filter on these connections and save the probe path information to a CSV file.(read more)![]()
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Virtuoso - The Next Overture: Introducing Simulation Driven Routing
The new release of the Virtuoso platform (ICADVM18.1) offers groundbreaking analysis capabilities and an innovational new simulation-driven interactive routing for more robust and efficient design implementation as well as extending our support for the most advanced users.(read more)![]()
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Virtuosity: How to Run a Multi-Technology Simulation (MTS)?
Are you looking for some hands-on experience with running multi-technology simulation in Virtuoso ADE Explorer and Virtuoso ADE Assembler?
In today’s fast-shrinking technology, we often have situations where we need to design custom IC system-in-packages (SiP). But, here comes the challenge – how to design these ICs using different technologies in a single design environment and analyze their responses when there are library name collisions along with the model name collisions.(read more)![]()
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Virtuoso IC6.1.7 ISR20 and ICADV12.3 ISR20 Now Available
The IC6.1.7 ISR20 and ICADV12.3 ISR20 production releases are now available for download. To find out more, click here…(read more)![]()
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Virtuosity: Let's Have Fun with ADE Debugging – Part 1
Over the years, we have seen our customers’ usage of ICRPs increase dramatically. It is now quite common to run 1000s of simulation points using 100s of ICRPs. And as this usage has increased, one of the challenges that has emerged is how to debug issues with ICRPs and job distribution, which is the topic of my write-up. So, what is it that I’m trying to address? Does the following sound familiar?
User hits green button in ADE, expects simulations to run and see results.
However, no simulation is starting. Why?
Or, one or more simulations fail, or, one or more measurements fail. User wants to find out what happened?
Or, things are running, but seem to take an excessive amount of time (usually not the actual simulation time, but rather setup time or time to obtain results).
How can we debug what’s wrong?
The objective of these slides is to equip everyone with a baseline set of tools and information to be used when investigating issues in ADE. These slides can serve as a very good reference material when faced with job distribution issues in ADE. Through this and my future blogs on debugging, I’ll attempt to use the tools and recipes from the slides and apply these to real life situations.(read more)![]()
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Virtuoso Video Diary: What's this Net Connected to?
Meet the Virtuoso Schematic Editor L Probes assistant, a dockable assistant where you can identify connections that exist for a net, filter on these connections and save the probe path information to a CSV file.(read more)![]()
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Virtuosity: A Guide to Bindkeys for Interactive and Assisted Routing Commands
I'm sure you are well-versed with the benefits of using bindkeys. So, to have a better user experience, find out more about the bindkeys that we provide for Virtuoso interactive and assisted routing commonly-used commands.(read more)![]()
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Virtuoso: The Next Overture - Virtuoso RF Solution for High Frequency Product Designs
The new release of the Virtuoso platform (ICADVM18.1) offers groundbreaking analysis capabilities and an innovational new simulation-driven layout for more robust and efficient design implementation as well as extending our support for the most advanced process technologies. With this solution, we are able to significantly improve productivity through advanced methodologies and provide the most comprehensive set of solutions in the industry with an interoperable flow across chip, package, module and board.
Every once in a while, a new technology, an old problem, and a big idea turn into an innovation.
Dean Kamen
The latest Advanced Methodology Virtuoso release (ICADVM18.1) introduces Virtuoso® RF Solution that allows you to create modules and packages in Virtuoso by leveraging new package design capabilities.
The solution removes a long-standing problem caused by the use of disparate design tools for IC design versus module and package design. Virtuoso RF Solution provides an integrated co-design cockpit for in-concert editing of different fabrics from IC to modules and packages through:
- Support for multiple IC and packaging technologies
- True golden schematic-driven design flow for the package or RF module design
- Built-in Layout versus Schematic (LVS) capabilities that guarantee design correctness
- Off-chip layout editing capabilities, such as device placement at any angle and routing, curved connect lines, and voids
- In-context viewing and editing of IC and package layout
- Integrated Electromagnetic solvers (MoM and FEM) to generate accurate and realistic models for simulations
Furthermore, the barrier between Virtuoso and Allegro platforms is lowered and will let you benefit from the unified flow while retaining the efficiency of the individual platforms.
Virtuoso RF Solution
Challenges of IC/Module/Package/Board Designs
Traditionally, IC and package designs are done in isolation with different design teams using their own tools. However, with the advent of complex designs in communication and automotive leading to 5G, combined with the pressure of the tight go-to market window, the traditional design flows can often lead to non-functional designs being taped out.
Current Module Assemble Stackup
To overcome some of the tool limitations, users create home-grown design flows that create subset models and manually stitch the models into the system schematic. However, when there is a need to incorporate multiple IC technologies, such as CMOS, SiGe, GaAs, GaN, InP, and so on, and filter technologies, such as SAW and BAW, on the same module, the home-grown solutions do not scale. Virtuoso RF solution addresses these challenges and supports a true multi-technology driven solution. This robust solution extends the Virtuoso schematic connectivity driven layout capabilities to RF module and package designs by allowing you to select critical subsets of the layout for accurate extraction and automatically stitch the models back into a golden schematic.
Schematic-Connectivity-Driven Layout Design
The built-in Layout Versus Abstract (LVA) and co-design capabilities will allow you to ensure that connectivity is maintained all the way from package balls to the IC bumps/pillars and inside the IC layout. To precisely account for high-frequency effects on design performance, it is required to use electromagnetic (EM) tools for accurate extraction. However, the use of EM tools increases the complexity of data exchange, which further makes it difficult to maintain and scale home-grown schematic-layout-extraction design flows. Ultimately, it becomes impossible to guarantee What You Simulate is What You Implement (WYSIWYI) in home-grown design flows!
Interactions Across Multiple EDA Tools
To answer that, Virtuoso RF solution encompasses electromagnetic solvers that are tightly integrated within the design environment. The EM solvers can be run directly in Virtuoso Layout without the need to create an EM layout. Also, the resultant S-Parameters are automatically inserted in an extracted view, which ensures that the golden schematic and layout are undisturbed.
Integrated EM Tools Providing Layered and Stacked EM Analysis Capability
This solution encourages greater collaboration across design disciplines and allows designers to focus on product innovation rather than the mundane details of data translation. It will inspire designers to innovate with the product designs instead of spending the time in translating designs across multiple tool boundaries.
Virtuoso RF Solution is the next generation design flow for the next generation of products. Sounds exciting? Stay tuned for our Virtuoso Advanced Nodes and Methodologies release ICADVM18.1.
Related Resources
What’s New in Virtuoso in ICADVM18.1
For more information on Cadence circuit design products and services, visit www.cadence.com.
Contact Us
For more information on the New Virtuoso Design Platform, or if you have any questions or feedback on the features covered in this blog, please contact team_virtuoso@cadence.com.If you would like to receive similar updates about new and exciting features being built into Virtuoso for our upcoming Advanced Nodes and Advanced Methodologies releases, type your email ID in the Subscriptions field at the top of the page and click SUBSCRIBE NOW.
Sutirtha Kabir and Deepti Mishra Gupta (Team Virtuoso)
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Virtuoso IC6.1.7 ISR20 and ICADV12.3 ISR20 Now Available
The IC6.1.7 ISR20 and ICADV12.3 ISR20 production releases are now available for download. To find out more, click here…(read more)![]()
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Virtuosity: Let's Have Fun with ADE Debugging – Part 1
Over the years, we have seen our customers’ usage of ICRPs increase dramatically. It is now quite common to run 1000s of simulation points using 100s of ICRPs. And as this usage has increased, one of the challenges that has emerged is how to debug issues with ICRPs and job distribution, which is the topic of my write-up. So, what is it that I’m trying to address? Does the following sound familiar?
User hits green button in ADE, expects simulations to run and see results.
However, no simulation is starting. Why?
Or, one or more simulations fail, or, one or more measurements fail. User wants to find out what happened?
Or, things are running, but seem to take an excessive amount of time (usually not the actual simulation time, but rather setup time or time to obtain results).
How can we debug what’s wrong?
The objective of these slides is to equip everyone with a baseline set of tools and information to be used when investigating issues in ADE. These slides can serve as a very good reference material when faced with job distribution issues in ADE. Through this and my future blogs on debugging, I’ll attempt to use the tools and recipes from the slides and apply these to real life situations.(read more)![]()
![]()
↧
Virtuoso Video Diary: What's this Net Connected to?
Meet the Virtuoso Schematic Editor L Probes assistant, a dockable assistant where you can identify connections that exist for a net, filter on these connections and save the probe path information to a CSV file.(read more)![]()
![]()
↧
Virtuosity: A Guide to Bindkeys for Interactive and Assisted Routing Commands
I'm sure you are well-versed with the benefits of using bindkeys. So, to have a better user experience, find out more about the bindkeys that we provide for Virtuoso interactive and assisted routing commonly-used commands.(read more)![]()
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Virtuoso IC6.1.7 ISR21 and ICADV12.3 ISR21 Now Available
The IC6.1.7 ISR21 and ICADV12.3 ISR21 production releases are now available for download at Cadence Downloads.
For information on supported platforms, compatibility with other Cadence tools, and details of issues resolved in each release, see:
The links above are functional at the time of publishing. If you encounter any links that are now obsolete, visit https://downloads.cadence.com and select the release name you are interested in to access the related files.
Here is a listing of some of the important updates made to IC6.1.7 ISR and ICADV12.3 ISR over the last few releases:
- Default Application to Open a Saved ADE State(from ISR21)
Specify a default application where you want to open a saved ADE state. Use these while migrating to ADE Explorer or ADE Assembler. - Wildcard Syntax for Saving PCells in Netlist(from ISR21)
Use wildcards to specify PCell operating point parameters on the Save Options form.
(ICADV12.3 Only) Display of Packet Name for WSP Tracks in Virtuoso Width Spacing Patterns (from ISR19)
Use custom display packets for WSP tracks.- New Single Schematic Driven Simulation and Layout Flow in Virtuoso System Design Platform (from ISR19)
Use a master schematic to drive both pre- and post-layout simulations and to create the package layout. - Enhanced eye diagram and measurement support (from ISR17)
Create a centered or custom eye diagram and calculate new eye measurements, such as Max Eye Height and Max Eye Width. - (ICADV12.3 Only) Area-based rule support in interactive routing (from ISR16)
Define different rules for different design areas and allow the edited shapes in an area to be automatically adjusted based on the specified rules. - Enhanced Update Binding support (from ISR16)
Bind layout instances based on a .sip file, if the .net file is not available for some reason.
For more details of these, and all other new and enhanced features introduced in this release, see:
Contact Us
Please send questions and feedback to virtuoso_rm@cadence.com.
To receive Virtuoso release announcements like this one, and other Virtuoso-related information, directly in your mailbox, type your email ID in the Subscriptions field at the top of the page and click SUBSCRIBE NOW.
Virtuoso Release Team
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Virtuoso IC6.1.8 and ICADVM18.1 Now Available
The IC6.1.8 and ICADVM18.1 production releases are now available for download. To find out what new and enhanced features do the releases bring, click here…(read more)![]()
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Virtuosity: Let's Have Fun with ADE Debugging – Part 1
Over the years, we have seen our customers’ usage of ICRPs increase dramatically. It is now quite common to run 1000s of simulation points using 100s of ICRPs. And as this usage has increased, one of the challenges that has emerged is how to debug issues with ICRPs and job distribution, which is the topic of my write-up. So, what is it that I’m trying to address? Does the following sound familiar?
User hits green button in ADE, expects simulations to run and see results.
However, no simulation is starting. Why?
Or, one or more simulations fail, or, one or more measurements fail. User wants to find out what happened?
Or, things are running, but seem to take an excessive amount of time (usually not the actual simulation time, but rather setup time or time to obtain results).
How can we debug what’s wrong?
The objective of these slides is to equip everyone with a baseline set of tools and information to be used when investigating issues in ADE. These slides can serve as a very good reference material when faced with job distribution issues in ADE. Through this and my future blogs on debugging, I’ll attempt to use the tools and recipes from the slides and apply these to real life situations.(read more)![]()
![]()
↧
Virtuoso Video Diary: What's this Net Connected to?
Meet the Virtuoso Schematic Editor L Probes assistant, a dockable assistant where you can identify connections that exist for a net, filter on these connections and save the probe path information to a CSV file.(read more)![]()
![]()
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