In Part 4 of the series, we looked at applying mismatch analysis as a design tool. In Part 5, we will continue to look at mismatch analysis by applying the technology  to other types of designs..

The first case we will look at is a circuit without a DC operating point. A dynamic comparator, see Figure 1, doesn’t have a quiescent operating point making it difficult to analyze.

In this case, the offset voltage is measured using transient analysis. A positive and a negative staircase is applied at the input and the input value which results in the output switching being recorded, the average value of input levels is the offset voltage. To increase the resolution of the offset voltage measurement, the step size needs to be small. In this case, the step size of the staircase ramp is 100mV. A Verilog A module was used as the signal source to generate the staircase, see Figure 2. For more details about measuring dynamic comparator offset Voltage, please see the ADC Verification Workshop Rapid Adoption Kit in Cadence online support.

Looking at the comparator, we would expect that the mismatch of the p-channel input transistors is the primary source of offset voltage.  After the Monte Carlo analysis, we will use scatter plots showing the random variable causing mismatch for three transistors: NM2, NM3, and NM4, see Figure 3a. For the devices in the differential pair, NM2 and NM3, we can see that there is correlation between the offset voltage and the input transistors, the correlation coefficient is r about 0.5. For the current source transistor, NM4, there is no correlation, the correlation coefficient r about 0, between the offset voltage and the transistor’s variation. So, the scatter plots are consistent with our expectations about how the devices are impacted and the statistical variation.

Again, we can see the utility and the limitations of the scatter plot. Qualitatively the scatter plot allows us to visualize the relationship between the inputs, statistical variables, and the outputs measured values. However, it is difficult to extract quantitative information from the results. So, while we can use scatter plots to confirm what we already know, they don’t really provide any additional information to designers.

We will use mismatch analysis to analyze the relationship between variations on offset voltage. The mismatch analysis results are shown in Figure 4. Again, we see that offset voltage has a non-linear, second-order relationship with the statistical variables. We can also see that most of the variation, 99.935% is accounted for by the mismatch results. We can see that ~90% of the offset voltage is due to the input transistor variation. Mismatch analysis considers the variation at the statistical variable level: NM2.rn2 contributes 30%, NM3.rn2 contributes 29%, NM2.rn1 contributes 17%, and NM3.rn1 contributes 16%. While our naming convention could be more explicit, you can think about the variables as the individual contributions to variation: gate oxide thickness variation and gate length variation. Another observation is that there is another source of offset voltage variation, the cascode transistors, NM0 and NM1. While not significant, it useful to know that mismatch analysis has enough resolution to identify small contributors.

Mismatch analysis provides designers a tool to analyze the effect of mismatch qualitatively and quantatively.  

To summarize, the mismatch analysis is a useful tool to analyze the results of Monte Carlo analysis. In this case, we analyzed the effect of variation on a dynamic comparator. Traditionally it is difficult to analyze a dynamic comparator because it is not a linear circuit with a DC operating point. Perhaps more than anything else, the ability to analyze circuits that designers have not been able to analyze in the past is the true value of mismatch analysis.

In Part 3, we started to explore how to analyze the results of Monte Carlo analysis. In Part 4, we will consider the question, what is the relationship between process variation and the circuit’s performance variation? The tool for exploring the relationship process variation and circuit performance variation is mismatch analysis in the tool Virtuoso^® Variation Option (VVO). 

Let’s start by looking at a simple example that shows the sources of offset voltage of a two-pole operational amplifier, see Figure 1.

Figure 1: Two Pole Operational Amplifier

Looking at the design, we would expect that mismatch of the p-channel input transistors are the primary source of offset voltage. First, let’s look at the Monte Carlo simulation results for the op-amp, see Figure 2.

Figure 2: Monte Carlo Analysis Results

The results show that the offset voltage is ~7.3mV. While Monte Carlo analysis tells us how much offset voltage there is, it does not tell us anything about the source of the offset voltage or how much improvement can be achieved. So, what are the sources of the offset voltage? After Monte Carlo analysis, we can plot the relationship between threshold voltage of input p-channel transistors, M17 and PM5, and the n-channel transistors in the first stage load current mirror. The scatter plots in Figure 3 show that there is no correlation between threshold voltage and the offset voltage of the operational amplifier since the correlation between offset voltage and the device threshold voltages is effectively 0.

Figure 3: Scatter Plots, Threshold Voltage versus Offset Voltage

Now let’s try using contribution analysis, see Figure 4.

Figure 4: Mismatch Analysis Results

Mismatch analysis shows the relationship between the threshold voltage and the offset voltage. The reasons that the scatter plot showed no correlation was because it looks for linear correlation. Mismatch analysis reports that the dependency is second order, the label shows R^2, The results show that most of the variation, 99.997%, can be explained by the threshold variation of the M17, PM5, NM4, and NM6. The results also show that ~70% of the offset voltage variation is due to the p-channel variation, the contribution from M17 is 34%, and the contribution from PM5 is 34%. The other source of offset voltage variation is the n-channel threshold voltage contribution of 30%.

Let’s use this information and see if we can improve the design. Since the p-channel contributes most of the offset voltage, we will try an experiment. We will increase the p-channel transistor area by 16x, length by 4x and width by 4x, keeping the W/L ratio constant. Increasing the device size should decrease the effect of p-channel mismatch by a factor of four.

Figure 5: Monte Carlo Analysis with 16x P-Channel

The effect of scaling the p-channel transistors on the offset voltage of the op-amp is to reduce the offset voltage from 7.2mV to 3.7mV. Doing some math, the p-channel offset contribution is ~6.4mV and the n-channel contribution is ~3.3mV. Verifying the offset voltage, the initial offset voltage is (6.4²) + (3.3²) = 7.2mV. After device sizing, the offset voltage is ((6.4/4)²) + (3.3²) = 3.7mV.

This example shows how mismatch analysis can be used to understand the effect of process variation on circuit performance. While we understand qualitatively that input transistors are the primary contributor to offset voltage, mismatch analysis provides us a tool for qualitative analysis of variation. In the next blog, we will apply mismatch analysis to additional circuits.  

In the comments to blog #4, Frank Wiedmann asked about the correlation between the results of mismatch from Monte Carlo analysis and DC mismatch analysis. It is a fair question and here is a short blog to explore the topic. The example may not be realistic, but it is a useful for exploring the effects of mismatch on a circuit.  

Let’s start with a simple circuit—A resistively loaded differential amplifier with cascodes, shown in Figure 1. The process is the Cadence® 45nm GPDK. This test circuit gives us a good platform for exploring the effect of mismatch on circuit performance. The GPDK includes models for Monte Carlo analysis and the results are easy to share.

 Figure 1: Differential Amplifier

As background, DC mismatch is an analysis that estimates the effect of mismatch on circuit performance from a single simulation. It is considerably faster than using Monte Carlo analysis. The drawback is that only the DC operating point effect of mismatch is considered, so we could not use it for the dynamic comparator, see part 5. Originally, the model card needed to be modified for DC mismatch analysis. DC mismatch used different mismatch parameters than Monte Carlo analysis. Since about 2012, DC mismatch analysis reads either the stats block or Monte Carlo process variations. The original DC mismatch parameters are still supported for backwards compatibility. For Virtuoso® ADE Explorer users, look in the Analyses tab for dcmatch. One point to keep in mind is that DC match simulates the offset voltage at a specified output due to process variation, however, it can’t be used for derived measurements.

For the Monte Carlo analysis, Low-Discrepancy Sampling was used. To generate a "good" distribution, 1400 iterations were used. From experience, this number of iterations should give a reasonable approximation to the expected distribution. The standard deviation of the output offset voltage is 10.56mV. The Monte Carlo analysis results are compared with the dc mismatch analysis results in Table 1.

Figure 2: Output Offset Voltage Distribution

The DC Mismatch analysis was run using the stats option, that is, the statistical information in the stats block is used for the DC mismatch analysis.  

Table 1: Comparison of Monte Carlo and DC Mismatch Results      

The comparison results show that the offset voltages are close but are not quite identical. The difference in the results comes down to the approximation that is used when performing DC mismatch analysis. DC mismatch analysis assumes that the output distribution is Gaussian. The assumption allows us to estimate the variation without requiring the many iterations required by Monte Carlo to calculate the actual distribution. This is an example where the assumption breaks down because the tails of the distribution are not Gaussian. The output referred offset voltage is plotted using the normal quantile-quantile plot, shown in Figure 3. The results show that the tails of the distribution are not Gaussian, see the areas in the green boxes.

Figure 3: Quantile-quantile plot of Output Offset Voltage

One other item to notice is that DC mismatch and Monte Carlo mismatch analysis report the same contributors. The contributors are the random variables that result in the largest variation in the output offset voltage.

The summary is that DC mismatch provides a reasonable approximation to Monte Carlo mismatch results and can be used for predicting trends and worst-case corners. The limitation is that DC mismatch relies on the assumption that the distribution is Gaussian. As a result for signoff, Monte Carlo analysis is the appropriate choice.

In days of future past, we looked at DC mismatch analysis and compared it to Monte Carlo analysis for analyzing the effect of device mismatch on the offset voltage of a differential amplifier. We found that DC mismatch does provide good estimates of the effect of mismatch with the limitation that the offset voltage has a Gaussian distribution. Since DC mismatch analysis only needed a single simulation to generate an estimate, we can use it for design exploration. For example, when looking for the worst-case corner for offset voltage, we can use DC mismatch analysis to accelerate simulation time.    

Suppose that we wanted to find the device size that meets our design specification for offset voltage. Let’s start with the same differential amplifier and assume that the offset voltage should be 1mV. How can we find the optimum gate width for this offset voltage 1sigma value? One option would be to perform DC mismatch analysis and sweep the n-channel transistor gate width. Let’s set a specification of a target offset voltage of 1mV and look for the gate width that will meet our offset voltage specification.

Figure 1: Parametric Sweep of Device Size vs. Offset Voltage

In this case, we swept the number of fingers for input pair and can see that the we can significantly reduce the area without compromising the offset voltage of the amplifier.

There is actually one alternative to the parametric sweep approach for tuning offset voltage. We can use mismatch analysis to perform the same task. In the Mismatch Contribution window, you can click on the Mismatch Tuner icon, see the red box on Figure 2.  

Figure 2: Using Mismatch Tuner to Size Transistors for Offset Voltage

When you click on the Mismatch Tuner icon, you get slider bars that you can adjust and the results in the Contribution Analysis window are updated. What we see here is that by reducing the gate width of the input transistors by 60%, then the offset voltage is 1mV. This result is consistent with the results of the parametric sweep of DC mismatch analysis. We can reduce the size of the input transistors by 60% and still meet our objectives for offset voltage.

 So, which method should I use? If all you are interested in is offset voltage of a linear analog circuit, then using DC mismatch with parametric sweep may be sufficient. However, in most other cases, this option is not available. Consider the dynamic comparator, it does not have a quiescent operating point so we can’t use DC mismatch to estimate the input stage scaling. In this case, mismatch tuning can be used. Suppose you need to make a choice to achieve a 500uV offset voltage, you can either scale the devices or add additional circuitry to calibrate out the offset. After running Monte Carlo analysis, see figure 3, the current offset voltage of the comparator is about 1mv, good but not good enough to meet the target. 

Figure 3: Dynamic Comparator Offset Voltage

So, let’s try using the mismatch tuner, see Figure 4. In this case, we see that we need to increase the device size by 4x to reduce the offset voltage level to an acceptable level. Based on this result, the designer needs to decide which approach to take: scaling the input devices, or adding an offset calibration, to better optimize area and power. So, we can use mismatch tuning to give us insight into how variation impacts offset voltage. Another use case to consider is suppose you have several parameters to trade-off: offset voltage, power supply rejection ratio, common-mode rejection ratio, and bandwidth. In this case, mismatch tuning allows you to envision interaction between device scaling and multiple parameters. So, while the two approaches overlap, using the mismatch tuner is a more general solution for analyzing the effect of mismatch on circuit performance.

Figure 4: Dynamic Comparator Offset Voltage Mismatch Tuning

One thing to keep in mind when using either dc mismatch analysis or mismatch tuning is that these techniques rely on mathematical techniques to estimate the effect of mismatch. These results should be verified with Monte Carlo analysis. In this case, after using mismatch tuning the results were checked. Before sizing the offset voltage was 938uV. Mismatch tuning suggested that by increasing the device size by about 4x, the offset voltage would be reduced to 480uV. Monte Carlo analysis shows that the actual offset voltage after tuning was 406uV, see figure 5. 

Figure 5: Dynamic Comparator Offset Voltage Monte Carlo Results after mismatch tuning

Over the last two blogs, we have looked at DC mismatch analysis. In the previous blog, we compared the results from dc mismatch analysis to Monte Carlo analysis as a tool for estimating offset voltage. Then in this blog we looked at using dc mismatch as a design tool to improve our design. In the next blog, we will take a similar look at AC mismatch analysis.         

In order to drive high current and to minimize routing resistivity, it is desirable to draw wide wires. But, in mature nodes, maximum width or maximum density constraints on some metal layers prevent the designers to create wide wires. Another challenge when working with designs at advanced nodes less than 22nm is that it is only possible to route with wires at minimum width. This leads to situations where the current density or the max resistivity cannot be met.

A solution to this is: Stranded Wire

What is a Stranded Wire?

To describe stranded wire in layman's language:

Stranded Wire is composed of a number of small wires bundled or wrapped together to form a larger conductor. See the figure below.

So, in interactive routing, stranded wire is an easy way to create multiple wires at the same time on same net with built-in features to control resistance and metal density. The stranded wire feature is available in Layout XL, GXL, and EAD tiers and was introduced in the IC6.1.7 and ICADV 12.3 ISR9 releases. To access the Create Stranded Wire command, choose Create – Wiring – Stranded Wire. 

A stranded wire can be created from the following starting points:

• An empty space
• An existing single pin
• An existing wire or via
• An existing width spacing pattern

You can create the following kind of structure by using the Create Stranded Wire command.

New Videos

Did you know that we retain only 10% of what we read and 95% of what we see?

Therefore, to help you understand and get started with the Stranded Wire new features easily, we bring to you some interesting and informative videos on this topic.

Stranded Wire Support in Virtuoso and Virtuoso Advanced Nodes

This video demonstrates the basic features and bindkey controls of stranded wire.

• What is a stranded wire?
• Why do we need a stranded wire in Layout?
• How to create a stranded wire in Virtuoso layout?
• What are the stranded wire bindkey controls?
• How to terminate a stranded wire?

Stranded Wire Additional Editing Features

This video demonstrates the following editing features of stranded wire.

• Inserting Vias Automatically on Pins and Overlaps
• Using the Stranded Wire Context-sensitive Menu
• Tapering in Stranded Wire
• Creating a Stranded Wire from Tieout

Stranded Wire Advanced Node Editing Features

This video demonstrates the following editing features of stranded wire for advanced nodes.

• WSP Support in Stranded Wire
• Automatic Via Insertion at Bends
• Blockage Avoidance
• Interactive Coloring in Stranded Wire

Related Resources

• Virtuoso Space-based Router User Guide

  • Working with Stranded Wires

  • Interactive Coloring for Create Stranded Wire

• Virtuoso Layout Suite SKILL Reference

  • leHiCreateStrandedWire

• Environment Variables

  • weStrandedAlignCollinearMode

  • weStrandedColorMode

  • weStrandedLadderAtTurn

  • weStrandNum

  • weStrandSpacing

 Note: For more information on Cadence circuit design products and services, visit www.cadence.com.

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Virtuoso Video Diary is an online journal that relays information about Virtuoso videos that are available in the Cadence Online Support Video Library. Hundreds of interesting videos on a wide variety of new and exciting Virtuoso features have already been created. Virtuoso Video Diary brings you direct links to these videos and other related material, on regular basis. Click Subscribe to visit the Subscription box at the top of the page in which you can submit your e-mail address to receive notifications about our latest Video Diary posts.

Happy Reading!

Parul Agarwal

In days of future past, we looked at DC mismatch analysis and compared it to Monte Carlo analysis for analyzing the effect of device mismatch on the offset voltage of a differential amplifier. We found that DC mismatch does provide good estimates of the effect of mismatch with the limitation that the offset voltage has a Gaussian distribution. Since DC mismatch analysis only needed a single simulation to generate an estimate, we can use it for design exploration. For example, when looking for the worst-case corner for offset voltage, we can use DC mismatch analysis to accelerate simulation time.    

Suppose that we wanted to find the device size that meets our design specification for offset voltage. Let’s start with the same differential amplifier and assume that the offset voltage should be 1mV. How can we find the optimum gate width for this offset voltage 1sigma value? One option would be to perform DC mismatch analysis and sweep the n-channel transistor gate width. Let’s set a specification of a target offset voltage of 1mV and look for the gate width that will meet our offset voltage specification.

Figure 1: Parametric Sweep of Device Size vs. Offset Voltage

In this case, we swept the number of fingers for input pair and can see that the we can significantly reduce the area without compromising the offset voltage of the amplifier.

There is actually one alternative to the parametric sweep approach for tuning offset voltage. We can use mismatch analysis to perform the same task. In the Mismatch Contribution window, you can click on the Mismatch Tuner icon, see the red box on Figure 2.  

Figure 2: Using Mismatch Tuner to Size Transistors for Offset Voltage

When you click on the Mismatch Tuner icon, you get slider bars that you can adjust and the results in the Contribution Analysis window are updated. What we see here is that by reducing the gate width of the input transistors by 60%, then the offset voltage is 1mV. This result is consistent with the results of the parametric sweep of DC mismatch analysis. We can reduce the size of the input transistors by 60% and still meet our objectives for offset voltage.

 So, which method should I use? If all you are interested in is offset voltage of a linear analog circuit, then using DC mismatch with parametric sweep may be sufficient. However, in most other cases, this option is not available. Consider the dynamic comparator, it does not have a quiescent operating point so we can’t use DC mismatch to estimate the input stage scaling. In this case, mismatch tuning can be used. Suppose you need to make a choice to achieve a 500uV offset voltage, you can either scale the devices or add additional circuitry to calibrate out the offset. After running Monte Carlo analysis, see figure 3, the current offset voltage of the comparator is about 1mv, good but not good enough to meet the target. 

Figure 3: Dynamic Comparator Offset Voltage

So, let’s try using the mismatch tuner, see Figure 4. In this case, we see that we need to increase the device size by 4x to reduce the offset voltage level to an acceptable level. Based on this result, the designer needs to decide which approach to take: scaling the input devices, or adding an offset calibration, to better optimize area and power. So, we can use mismatch tuning to give us insight into how variation impacts offset voltage. Another use case to consider is suppose you have several parameters to trade-off: offset voltage, power supply rejection ratio, common-mode rejection ratio, and bandwidth. In this case, mismatch tuning allows you to envision interaction between device scaling and multiple parameters. So, while the two approaches overlap, using the mismatch tuner is a more general solution for analyzing the effect of mismatch on circuit performance.

Figure 4: Dynamic Comparator Offset Voltage Mismatch Tuning

One thing to keep in mind when using either dc mismatch analysis or mismatch tuning is that these techniques rely on mathematical techniques to estimate the effect of mismatch. These results should be verified with Monte Carlo analysis. In this case, after using mismatch tuning the results were checked. Before sizing the offset voltage was 938uV. Mismatch tuning suggested that by increasing the device size by about 4x, the offset voltage would be reduced to 480uV. Monte Carlo analysis shows that the actual offset voltage after tuning was 406uV, see figure 5. 

Figure 5: Dynamic Comparator Offset Voltage Monte Carlo Results after mismatch tuning

Over the last two blogs, we have looked at DC mismatch analysis. In the previous blog, we compared the results from dc mismatch analysis to Monte Carlo analysis as a tool for estimating offset voltage. Then in this blog we looked at using dc mismatch as a design tool to improve our design. In the next blog, we will take a similar look at AC mismatch analysis.         

Systems on Chip, or SoCs as they’re more commonly called, have become increasingly more complex, and incorporate a dizzying array of functionality to keep up with the evolving trends of technology. Today’s SoCs are humongous multi-billion-gate designs with huge memories to enable complex and high-performance functions that are executed on them. It is quite common to have about 40% of an SoC’s real estate used for Static Random Access Memory (SRAM). SRAM design is a complex and highly sensitive process, and what we want to design in the silicon is often different from what actually comes out of the manufacturing process. This is due to Advanced On-Chip Variations, or AOCVs.

AOCVs occur in the device manufacturing processes, and there are two kinds:

1. Systematic Variations: These are caused by variations in gate oxide thickness, implant doses and metal or dielectric thickness. They are deterministic in nature, and exhibit spatial correlation – i.e., they are proportional to the cell location of the path being analyzed.
2. Random Variations: These are random, as the name suggests, and therefore are non-deterministic. They are proportional to the logic depth of the path being analyzed, and tend to statistically cancel each other out given a long enough path.

As can be deduced, the effects of these variations are getting more pronounced as process geometries are shrinking, and so dealing with them in an effective manner is crucial to the proper functioning of an SoC. And therein lies the rub.

Traditional Solutions for AOCVs in SRAMs

AOCVs need to be modeled effectively, so their effects can be taken into account for the ultimate SRAM design to be successful. This means the design needs to be simulated to account for the random and deterministic process variations. Most companies deal with this in one of the following two ways:

1. Running a Monte Carlo simulation on the full memory instance RC extracted netlist

This approach involves creating a simulatable instance netlist from the instance schematic, and running Monte Carlo simulations on the complete netlist, multiple times. This will give us the most accurate results. However, this is an incredibly CPU and memory intensive approach, with run times lasting several days. Additionally, it will require huge runtime memory requirements and will need bigger LSF machines.

2. Run Monte Carlo simulations on the critical path RC netlist

This approach involves reducing the netlist drastically by identifying repetitive cells in the memory and replacing them with a load model. Then you create a critical path schematic for each component to be simulated and run Monte Carlo. While this approach is definitely much faster than the previous approach, it still involves several thousand nodes and instances, and runtime is still in the order of a few days. Additionally, it requires time to create critical path schematics for different components and to ensure the setup is correct. Creating a critical path involves manual effort and is error prone, making it a less than ideal solution.

So what is a designer to do?

Enter, the approach used by our customer, Invecas. Their solution is based entirely on the Legato Memory Solution, specifically Liberate-MX runs, with Spectre simulations. It relies on re-suing the characterization database from Liberate-MX runs. This means, there is no additional time spent on setting up the environment. It also involves reusing the partition netlist created by the Liberate-MX flow. Liberate has the inbuilt intelligence of identifying the dynamic partition, and activity factor. This approach results in the least amount of runtime and memory required.

So how does this work?

Liberate runs a Fast-SPICE tool under the hood to identify the worst-case path that is active and toggling, and extracts only that path to work on. Then an accurate SPICE run is performed, to provide the accurate .libs. Generating these accurate .libs is already included in the Liberate MX flow and available today. Invecas then modified this flow for AOCV, by taking this partition, with all the accompanying setups and nodes, and adding a couple of commands for Monte Carlo runs. The script now runs Monte Carlo on the greatly reduced partition, and returns AOCV models with all the derating values in a matter of hours, instead of days, or even weeks.

The comparison of results between the three approaches can be summarized below.

The side-by-side testing clearly shows, that the Invecas method using the Legato Memory Solution has greatly reduced the number of devices, nodes and RC elements that the Monte Carlo run uses, from several million, to a few thousand. This automatically reduces the runtime and memory requirements by several orders of magnitude, thereby solving the biggest problem faced by the designers today.

Please visit our page to find out more about this process, or to read about the Cadence Legato Memory Solution.